gem5.prebuilt.riscvmatched.riscvmatched_cache module

class gem5.prebuilt.riscvmatched.riscvmatched_cache.RISCVMatchedCacheHierarchy(l2_size: str)

Bases: AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy

A cache setup where each core has a private L1 Data and Instruction Cache, and a shared L2 cache.

The HiFive board has a partially inclusive cache hierarchy, hence this hierarchy is chosen.

The details of the cache hierarchy are in Table 7, page 36 of the datasheet.

• L1 Instruction Cache:

  • 32 KiB 4-way set associative

• L1 Data Cache

  • 32 KiB 8-way set associative

• L2 Cache

  • 2 MiB 16-way set associative

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_cpu_side_port() → Port

get_mem_side_port() → Port

incorporate_cache(board: AbstractBoard) → None

Incorporates the caches into a board.

Each specific hierarchy needs to implement this function and will be unique for each setup.

Parameters:

board – The board in which the cache heirarchy is to be incorporated.