gem5.prebuilt.riscvmatched.riscvmatched_core module

class gem5.prebuilt.riscvmatched.riscvmatched_core.U74BP(**kwargs)

Bases: TournamentBP

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74CPU(**kwargs)

Bases: RiscvMinorCPU

The fetch, decode, and execute stage parameters from the ARM HPI CPU This information about the CPU can be found on page 15 of gem5_rsk_gem5-21.2.pdf at https://github.com/arm-university/arm-gem5-rsk

The parameters that are changed are: - threadPolicy:

This is initialized to “SingleThreaded”.

  • decodeToExecuteForwardDelay:

    This is changed from 1 to 2 to avoid a PMC address fault.

  • fetch1ToFetch2BackwardDelay:

    This is changed from 1 to 0 to better match hardware performance.

  • fetch2InputBufferSize:

    This is changed from 2 to 1 to better match hardware performance.

  • decodeInputBufferSize:

    This is changed from 3 to 2 to better match hardware performance.

  • decodeToExecuteForwardDelay:

    This is changed from 2 to 1 to better match hardware performance.

  • executeInputBufferSize:

    This is changed from 7 to 4 to better match hardware performance.

  • executeMaxAccessesInMemory:

    This is changed from 2 to 1 to better match hardware performance.

  • executeLSQStoreBufferSize:

    This is changed from 5 to 3 to better match hardware performance.

  • executeBranchDelay:

    This is changed from 1 to 2 to better match hardware performance.

  • enableIdling:

    This is changed to False to better match hardware performance.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74Core(core_id)

Bases: BaseCPUCore

U74Core models the core of the HiFive Unmatched board. The core has a single thread. The latencies of the functional units are set to values found in Table 8 on page 40.

  • IntFU: 1 cycle

  • IntMulFU: 3 cycles

  • IntDivFU: 6 cycles (NOTE: latency is variable, but is set to 6 cycles)

  • MemReadFU: 2 cycles

  • MemWriteFU: 2 cycles

The branch predictor is a TournamentBP, based on Section 4.2.5 on page 38.

  • BTBEntries: 32 entries

  • RASSize: 12 entries

  • IndirectSets: 16 sets

  • localPredictorSize: 16384

  • globalPredictorSize: 16384

  • choicePredictorSize: 16384

  • localCtrBits: 4

  • globalCtrBits: 4

  • choiceCtrBits: 4

  • localHistoryTableSize: 4096 B

Note

The TournamentBP deviates from the actual BP. This configuration performs the best in relation to the hardware.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74FUPool(**kwargs)

Bases: MinorFUPool

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74FloatSimdFU(**kwargs)

Bases: MinorDefaultFloatSimdFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74IntDivFU(**kwargs)

Bases: MinorDefaultIntDivFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74IntFU(**kwargs)

Bases: MinorDefaultIntFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74IntMulFU(**kwargs)

Bases: MinorDefaultIntMulFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74MemReadFU(**kwargs)

Bases: MinorDefaultMemFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74MemWriteFU(**kwargs)

Bases: MinorDefaultMemFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74MiscFU(**kwargs)

Bases: MinorDefaultMiscFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.prebuilt.riscvmatched.riscvmatched_core.U74PredFU(**kwargs)

Bases: MinorDefaultPredFU

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []