gem5.prebuilt.riscvmatched.riscvmatched_board module

class gem5.prebuilt.riscvmatched.riscvmatched_board.RISCVMatchedBoard(clk_freq: str = '1.2GHz', l2_size: str = '2MiB', is_fs: bool = False)

Bases: AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload

A board capable of full system simulation for RISC-V

At a high-level, this is based on the HiFive Unmatched board from SiFive. Based on : src/python/gem5/components/boards/riscv_board.py

This board assumes that you will be booting Linux for fullsystem emulation.

The frequency of the RTC for the system is set to 1MHz. Details can be found on page 77, section 7.1 of the datasheet.

Datasheet for inbuilt params can be found here: https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
generate_device_tree(outdir: str) → None

Creates the dtb and dts files.

Creates two files in the outdir: device.dtb and device.dts

Parameters:

outdir – Directory to output the files

get_default_kernel_args() → List[str]

Returns a default list of arguments for the workload kernel. We assume the following strings may be used as placeholders, to be replaced when set_kernel_disk_workload is executed:

  • {root_value} : set to get_default_kernel_root_val().

Returns:

A default list of arguments for the workload kernel.

get_disk_device()

Set a default disk device, in case user does not specify a disk device.

Returns:

The disk device.

get_dma_ports() → List[Port]

Get the board’s Direct Memory Access ports. This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

Returns:

A List of the Direct Memory Access ports.

get_io_bus() → IOXBar

Get the board’s IO Bus.

This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

The I/O bus is a non-coherent bus (in the classic caches). On the CPU side, it accepts requests meant for I/O devices. On the memory side, it forwards these requests to the devices (e.g., the interrupt controllers on each core).

Returns:

The I/O Bus.

get_mem_side_coherent_io_port() → Port

Get the memory-side coherent I/O port.

This abstract method must be implemented if has_coherent_io is True.

This returns a port (not a bus) that should be connected to a CPU-side port for which coherent I/O (DMA) is issued.

has_coherent_io() → bool

Determine whether the board needs coherent I/O

Returns:

True if the board needs coherent I/O, False otherwise.

has_dma_ports() → bool

Determine whether the board has DMA ports or not.

Returns:

True if the board has DMA ports, otherwise False.

has_io_bus() → bool

Determine whether the board has an IO bus or not.

Returns:

True if the board has an IO bus, otherwise False.

set_kernel_disk_workload(kernel: AbstractResource, disk_image: AbstractResource, bootloader: AbstractResource | None = None, readfile: str | None = None, readfile_contents: str | None = None, kernel_args: List[str] | None = None, exit_on_work_items: bool = True) → None

This function allows the setting of a full-system run with a Kernel and a disk image.

Parameters:

  • kernel – The kernel to boot.

  • disk_image – The disk image to mount.

  • bootloader – The current implementation of the ARM board requires three resources to operate – kernel, disk image, and, a bootloader.

  • readfile – An optional parameter stating the file to be read by by m5 readfile.

  • readfile_contents – An optional parameter stating the contents of the readfile file. If set with readfile, the contents of readfile will be overwritten with readfile_contents, otherwise a new file will be created with the value of readfile_contents.

  • kernel_args – An optional parameter for setting arguments to be passed to the kernel. By default set to get_default_kernel_args().

  • exit_on_work_items – Whether the simulation should exit on work items. True by default.

  • checkpoint – The checkpoint directory. Used to restore the simulation to that checkpoint.

gem5.prebuilt.riscvmatched.riscvmatched_board.U74Memory()

Memory for the U74 board.

DDR4 Subsystem with 16GiB of memory.

Starts at 0x80000000.

Details at: Section 23, page 195 of the datasheet.

Returns:

ChanneledMemory