gem5.components.boards.abstract_board module

class gem5.components.boards.abstract_board.AbstractBoard(clk_freq: str, processor: AbstractProcessor, memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy | None)

Bases: object

The abstract board interface.

Boards are used as the object which can connect together all other components. This abstract class defines the external interface that other boards must provide. Boards can be specialized for different ISAs or system designs (e.g., core counts, cache types, memory channels, I/O devices, etc).

In addition to providing the place that system components are connected, the board also exposes an interface for the caches, processor, and memory to interact.

The board also exposes an interface to set up I/O devices which needs to be specialized for each ISA and/or platform.

Board inherits from System and can therefore be used as a System SimObject when required.

connect_system_port(port: Port) → None

get_cache_hierarchy() → AbstractCacheHierarchy | None

Get the cache hierarchy connected to the board.

Returns:

The cache hierarchy.

get_cache_line_size() → int

Get the size of the cache line.

Returns:

The size of the cache line size.

get_clock_domain() → ClockDomain

Get the clock domain.

Returns:

The clock domain.

get_devices()

Get the devices connected to the board.

Currently, this is only used for GPUs by the ViperBoard.

Returns:

The devices connected to the board or None.

abstract get_dma_ports() → List[Port]

Get the board’s Direct Memory Access ports. This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

Returns:

A List of the Direct Memory Access ports.

abstract get_io_bus() → IOXBar

Get the board’s IO Bus.

This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

The I/O bus is a non-coherent bus (in the classic caches). On the CPU side, it accepts requests meant for I/O devices. On the memory side, it forwards these requests to the devices (e.g., the interrupt controllers on each core).

Returns:

The I/O Bus.

get_mem_ports() → Sequence[Tuple[AddrRange, Port]]

Get the memory ports exposed on this board

Note

The ports should be returned such that the address ranges are in ascending order.

abstract get_mem_side_coherent_io_port()

Get the memory-side coherent I/O port.

This abstract method must be implemented if has_coherent_io is True.

This returns a port (not a bus) that should be connected to a CPU-side port for which coherent I/O (DMA) is issued.

get_memory() → AbstractMemory

Get the memory (RAM) connected to the board.

Returns:

The memory system.

get_processor() → AbstractProcessor

Get the processor connected to the board.

Returns:

The processor.

abstract has_coherent_io() → bool

Determine whether the board needs coherent I/O

Returns:

True if the board needs coherent I/O, False otherwise.

abstract has_dma_ports() → bool

Determine whether the board has DMA ports or not.

Returns:

True if the board has DMA ports, otherwise False.

abstract has_io_bus() → bool

Determine whether the board has an IO bus or not.

Returns:

True if the board has an IO bus, otherwise False.

is_fullsystem() → bool

Returns True if the board is to be run in FS mode. Otherwise the board is to be run in Se mode. An exception will be thrown if this has not been set.

This function is used by the Simulator module to setup the simulation correctly.

is_workload_set() → bool

set_is_workload_set(is_set: bool) → None

set_mem_mode(mem_mode: MemMode) → None

Set the memory mode of the board.

Parameters:

mem_mode – The memory mode the board is to be set to.

set_workload(workload: WorkloadResource) → None

Set the workload for this board to run.

This function will take the workload specified and run the correct workload function (e.g., set_kernel_disk_workload) with the correct parameters

Parameters:

workload – The workload to be set to this board.