gem5.components.processors.base_cpu_core module¶

class gem5.components.processors.base_cpu_core.BaseCPUCore(core: BaseCPU, isa: ISA)¶

An stdlib AbstractCore subclass which wraps a BaseCPU SimObject type.

add_pc_tracker_probe(target_pair: List[PcCountPair], manager: PcCountTrackerManager) → None¶

connect_dcache(port: Port) → None¶

This function should connect the response port from the data cache to the right request port on the core.

connect_icache(port: Port) → None¶

This function should connect the response port from the instruction cache to the right request port on the core.

connect_interrupt(interrupt_requestor: Port | None = None, interrupt_responce: Port | None = None) → None¶

Connect the core interrupts to the interrupt controller

This function is usually called from the cache hierarchy since the optional ports can be implemented as cache ports.

connect_walker_ports(port1: Port, port2: Port) → None¶

Connect the response port from itb and dtb to their respective request ports in the core.

Parameters:

get_mmu() → BaseMMU¶

Return the MMU for this core.

This is used in the board to setup system-specific MMU settings.

is_kvm_core() → bool¶: KVM cores need setup differently than other cores. Frequently it’s useful to know whether a core is a KVM core or not. This function helps with this.

requires_send_evicts() → bool¶: True if the CPU model or ISA requires sending evictions from caches to the CPU. Scenarios warrant forwarding evictions to the CPU: 1. The O3 model must keep the LSQ coherent with the caches. 2. The x86 mwait instruction is built on top of coherence. 3. The local exclusive monitor in ARM systems.

gem5.components.processors.base_cpu_core.html