gem5.components.boards.arm_board module

class gem5.components.boards.arm_board.ArmBoard(clk_freq: str, processor: ~gem5.components.processors.abstract_processor.AbstractProcessor, memory: ~gem5.components.memory.abstract_memory_system.AbstractMemorySystem, cache_hierarchy: ~gem5.components.cachehierarchies.abstract_cache_hierarchy.AbstractCacheHierarchy, platform: ~m5.objects.RealView.VExpress_GEM5_Base = <m5.objects.RealView.VExpress_GEM5_Foundation object>, release: ~m5.objects.ArmSystem.ArmRelease = <m5.objects.ArmSystem.ArmDefaultRelease object>)

Bases: ArmSystem, AbstractBoard, KernelDiskWorkload

A board capable of full system simulation for ARM instructions. It is based ARMv8.

The board is based on Arm Motherboard Express uATX (V2M-P1), Arm CoreTile Express A15x2 (V2P-CA15) and on Armv8-A FVP Foundation platform v11.8, depending on the simulated platform. These boards are parts of ARM’s Versatile(TM) Express family of boards.

Limitations * stage2 walker ports are ignored. * KVM cores only work with VExpress_GEM5_V1

abstract = False
connect_system_port(port: Port) → None
createCCObject()

We override this function as it is called in m5.instantiate. This means we can insert a check to ensure the _connect_things function has been run.

cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
get_default_kernel_args() → List[str]

Returns a default list of arguments for the workload kernel. We assume the following strings may be used as placeholders, to be replaced when set_kernel_disk_workload is executed:

  • {root_value} : set to get_default_kernel_root_val().

Returns:

A default list of arguments for the workload kernel.

get_disk_device()

Set a default disk device, in case user does not specify a disk device.

Returns:

The disk device.

get_dma_ports() → List[Port]

Get the board’s Direct Memory Access ports. This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

Returns:

A List of the Direct Memory Access ports.

get_io_bus() → IOXBar

Get the board’s IO Bus.

This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

The I/O bus is a non-coherent bus (in the classic caches). On the CPU side, it accepts requests meant for I/O devices. On the memory side, it forwards these requests to the devices (e.g., the interrupt controllers on each core).

Returns:

The I/O Bus.

get_mem_ports() → Sequence[Tuple[AddrRange, Port]]

Get the memory ports exposed on this board

Note

The ports should be returned such that the address ranges are in ascending order.

get_mem_side_coherent_io_port() → Port

Get the memory-side coherent I/O port.

This abstract method must be implemented if has_coherent_io is True.

This returns a port (not a bus) that should be connected to a CPU-side port for which coherent I/O (DMA) is issued.

has_coherent_io() → bool

Determine whether the board needs coherent I/O

Returns:

True if the board needs coherent I/O, False otherwise.

has_dma_ports() → bool

Determine whether the board has DMA ports or not.

Returns:

True if the board has DMA ports, otherwise False.

has_io_bus() → bool

Determine whether the board has an IO bus or not.

Returns:

True if the board has an IO bus, otherwise False.