gem5.prebuilt.demo.riscv_demo_board module

class gem5.prebuilt.demo.riscv_demo_board.RiscvDemoBoard

Bases: RiscvBoard

This board is based on the X86DemoBoard.

This prebuilt RISCV board is used for demonstration purposes. It simulates an RISCV 1.4GHz dual-core system with a 4GiB DDR4_2400 memory system. A private L1, shared L2 cache hierarchy is set with a l1 data and instruction cache, each 64KiB with an associativity of 8, and a single bank l2 cache of 1MiB with an associativity of 16.

DISCLAIMER: This board is solely for demonstration purposes. This board is not known to be representative of any real-world system or produce reliable statistical results.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []