gem5.components.boards.riscv_board module

class gem5.components.boards.riscv_board.RiscvBoard(clk_freq: str, processor: AbstractProcessor, memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy)

Bases: AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload

A board capable of full system simulation for RISC-V.

At a high-level, this is based on the HiFive Unmatched board from SiFive.

This board assumes that you will be booting Linux.

Limitations * Only works with classic caches

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

generate_device_tree(outdir: str) → None

Creates the dtb and dts files.

Creates two files in the outdir: device.dtb and device.dts.

Parameters:

outdir – Directory to output the files.

get_default_kernel_args() → List[str]

Returns a default list of arguments for the workload kernel. We assume the following strings may be used as placeholders, to be replaced when set_kernel_disk_workload is executed:

• {root_value} : set to get_default_kernel_root_val().

Returns:

A default list of arguments for the workload kernel.

get_disk_device()

Set a default disk device, in case user does not specify a disk device.

Returns:

The disk device.

get_dma_ports() → List[Port]

Get the board’s Direct Memory Access ports. This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

Returns:

A List of the Direct Memory Access ports.

get_io_bus() → IOXBar

Get the board’s IO Bus.

This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

The I/O bus is a non-coherent bus (in the classic caches). On the CPU side, it accepts requests meant for I/O devices. On the memory side, it forwards these requests to the devices (e.g., the interrupt controllers on each core).

Returns:

The I/O Bus.

get_mem_side_coherent_io_port() → Port

Get the memory-side coherent I/O port.

This abstract method must be implemented if has_coherent_io is True.

This returns a port (not a bus) that should be connected to a CPU-side port for which coherent I/O (DMA) is issued.

has_coherent_io() → bool

Determine whether the board needs coherent I/O

Returns:

True if the board needs coherent I/O, False otherwise.

has_dma_ports() → bool

Determine whether the board has DMA ports or not.

Returns:

True if the board has DMA ports, otherwise False.

has_io_bus() → bool

Determine whether the board has an IO bus or not.

Returns:

True if the board has an IO bus, otherwise False.