gem5.components.memory.simple module

Simple memory controllers

class gem5.components.memory.simple.SingleChannelSimpleMemory(latency: str, latency_var: str, bandwidth: str, size: str)

Bases: AbstractMemorySystem

A class to implement single channel memory system using SimpleMemory

This class takes latency, latency variation, and bandwidth and configures a memory with those values. It could be used for studies that do not target memory subsystem design.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_mem_ports() → Sequence[Tuple[AddrRange, Port]]

Get the ports to connect this memory system to the cache.

get_memory_controllers() → List[MemCtrl]

Get all of the memory controllers in this memory system.

get_size() → int

Returns the total size of the memory system.

incorporate_memory(board: AbstractBoard) → None

This function completes all of the necessary steps to add this memory system to the board.

set_memory_range(ranges: List[AddrRange]) → None

Set the total range for this memory system.

May pass multiple non-overlapping ranges. The total size of the ranges should match the size of the memory.

If this memory system is incompatible with the ranges, an exception will be raised.