gem5.components.memory.memory module

Channeled “generic” DDR memory controllers

class gem5.components.memory.memory.ChanneledMemory(dram_interface_class: Type[DRAMInterface], num_channels: int | str, interleaving_size: int | str, size: str | None = None, addr_mapping: str | None = None)

Bases: AbstractMemorySystem

A class to implement multi-channel memory system

This class can take a DRAM Interface as a parameter to model a multi channel DDR DRAM memory system.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_mem_interfaces() → List[DRAMInterface]

Get all memory interfaces in this memory system. Useful when creating physical memory objects.

get_mem_ports() → Sequence[Tuple[AddrRange, Port]]

Get the ports to connect this memory system to the cache.

get_memory_controllers() → List[MemCtrl]

Get all of the memory controllers in this memory system.

get_size() → int

Returns the total size of the memory system.

get_uninterleaved_range() → List[AddrRange]

Returns the range of the memory system without interleaving. This is useful when other components in the system want to interleave the memory range different to how the memory has interleaved them.

incorporate_memory(board: AbstractBoard) → None

This function completes all of the necessary steps to add this memory system to the board.

set_memory_range(ranges: List[AddrRange]) → None

Need to add support for non-contiguous non overlapping ranges in the future.