gem5.components.memory.dram_interfaces.wideio module

Interfaces for WideIO memory devices

These memory “interfaces” contain the timing,energy,etc parameters for each memory type and are usually based on datasheets for the memory devices.

You can use these interfaces in the MemCtrl object as the dram timing interface.

class gem5.components.memory.dram_interfaces.wideio.WideIO_200_1x128(**kwargs)

Bases: DRAMInterface

A single WideIO x128 interface (one command and address bus), with default timings based on an estimated WIO-200 8 Gbit part.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []