gem5.components.memory.dram_interfaces.lpddr5 module

Interfaces for LPDDR5 memory devices

These memory “interfaces” contain the timing,energy,etc parameters for each memory type and are usually based on datasheets for the memory devices.

You can use these interfaces in the MemCtrl object as the dram timing interface.

class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_5500_1x16_8B_BL32(**kwargs)

Bases: LPDDR5_5500_1x16_BG_BL32

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specification.

Starting with 5.5Gbps data rates and 8Gbit die.

Configuring for 8-bank mode, burst of 32.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_5500_1x16_BG_BL16(**kwargs)

Bases: LPDDR5_5500_1x16_BG_BL32

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specification Starting with 5.5Gbps data rates and 8Gbit die Configuring for 16-bank mode with bank-group architecture, burst of 16

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_5500_1x16_BG_BL32(**kwargs)

Bases: DRAMInterface

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specification.

Starting with 5.5Gbps data rates and 8Gbit die.

Configuring for 16-bank mode with bank-group architecture burst of 32, which means bursts can be interleaved.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_6400_1x16_8B_BL32(**kwargs)

Bases: LPDDR5_6400_1x16_BG_BL32

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specification.

6.4Gbps data rates and 8Gbit die.

Configuring for 8-bank mode, burst of 32.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_6400_1x16_BG_BL16(**kwargs)

Bases: LPDDR5_6400_1x16_BG_BL32

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specifcation.

6.4Gbps data rates and 8Gbit die.

Configuring for 16-bank mode with bank-group architecture, burst of 16.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
class gem5.components.memory.dram_interfaces.lpddr5.LPDDR5_6400_1x16_BG_BL32(**kwargs)

Bases: LPDDR5_5500_1x16_BG_BL32

A single LPDDR5 x16 interface (one command/address bus) for a single x16 channel with default timings based on initial JEDEC specification.

6.4Gbps data rates and 8Gbit die.

Configuring for 16-bank mode with bank-group architecture burst of 32, which means bursts can be interleaved.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []