gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy.html
gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy module¶
- class gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy.PrivateL1PrivateL2CacheHierarchy(l1d_size: str, l1i_size: str, l2_size: str, membus: BaseXBar | None = None)¶
Bases:
AbstractClassicCacheHierarchy,AbstractTwoLevelCacheHierarchyA cache setup where each core has a private L1 Data and Instruction Cache, and a private L2 cache.
- abstract = False¶
- cxx_exports = []¶
- cxx_extra_bases = []¶
- cxx_param_exports = []¶
- cxx_template_params = []¶
- get_cpu_side_port() Port¶
- get_mem_side_port() Port¶
- incorporate_cache(board: AbstractBoard) None¶
Incorporates the caches into a board.
Each specific hierarchy needs to implement this function and will be unique for each setup.
- Parameters:
board – The board in which the cache heirarchy is to be incorporated.