gem5.components.cachehierarchies.classic.no_cache.html

gem5.components.cachehierarchies.classic.no_cache module — gem5 documentation

gem5.components.cachehierarchies.classic.no_cache module¶

class gem5.components.cachehierarchies.classic.no_cache.NoCache(membus: BaseXBar | None = None)¶

Bases: AbstractClassicCacheHierarchy

No cache hierarchy. The CPUs are connected straight to the memory bus.

By default a SystemXBar of width 64bit is used, though this can be configured via the constructor.

Note

At present this does not work with FS. The following error is received:

abstract = False¶

cxx_exports = []¶

cxx_extra_bases = []¶

cxx_param_exports = []¶

cxx_template_params = []¶

get_cpu_side_port() → Port¶

get_mem_side_port() → Port¶

incorporate_cache(board: AbstractBoard) → None¶

Incorporates the caches into a board.

Each specific hierarchy needs to implement this function and will be unique for each setup.

Parameters:: board – The board in which the cache heirarchy is to be incorporated.