gem5.components.cachehierarchies.chi.private_l1_cache_hierarchy.html
gem5.components.cachehierarchies.chi.private_l1_cache_hierarchy module¶
- class gem5.components.cachehierarchies.chi.private_l1_cache_hierarchy.PrivateL1CacheHierarchy(size: str, assoc: int)¶
Bases:
AbstractRubyCacheHierarchyA single level cache based on CHI for RISC-V
This hierarchy has a split I/D L1 caches per CPU, a single directory (HNF), and as many memory controllers (SNF) as memory channels. The directory does not have an associated cache.
The network is a simple point-to-point between all of the controllers.
- abstract = False¶
- cxx_exports = []¶
- cxx_extra_bases = []¶
- cxx_param_exports = []¶
- cxx_template_params = []¶
- get_coherence_protocol()¶
Returns the coherence protocol used in the cache hierarchy.
- Returns:
The coherence protocol used in the cache hierarchy.
- incorporate_cache(board: AbstractBoard) None¶
Incorporates the caches into a board.
Each specific hierarchy needs to implement this function and will be unique for each setup.
- Parameters:
board – The board in which the cache heirarchy is to be incorporated.