gem5.components.processors.abstract_generator_core module

class gem5.components.processors.abstract_generator_core.AbstractGeneratorCore

Bases: AbstractCore

The abstract generator core

Generator cores are cores that can replace the processing cores to allow for testing computer systems in gem5. The abstract class AbstractGeneratorCore defines the external interface that every generator core must implement. Certain generator cores might need to extend this interface to fit their requirements.

abstract = False

connect_icache(port: Port) → None

Generator cores only have one request port which we will connect to the data cache not the icache. Just connect the icache to the PortTerminator here.

connect_interrupt(interrupt_requestor: Port | None = None, interrupt_responce: Port | None = None) → None

Since generator cores are not used in full system mode, no need to connect them to walker ports. Just pass here.

connect_walker_ports(port1: Port, port2: Port) → None

Since generator cores are not used in full system mode, no need to connect them to walker ports. connect them to PortTerminator here.

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_isa() → ISA

is_kvm_core() → bool

KVM cores need setup differently than other cores. Frequently it’s useful to know whether a core is a KVM core or not. This function helps with this.

set_workload(process: Process) → None

Generator cores do not need any workload assigned to them, as they generate their own synthetic workload (synthetic traffic). Just pass here.

Parameters:

process – The process to execute during simulation.

abstract start_traffic()

External interface to start generating the trace of addresses.

Depending on what SimObject is wrapped by this component this method might need be implemented.