gem5.components.boards.simple_board module

class gem5.components.boards.simple_board.SimpleBoard(clk_freq: str, processor: AbstractProcessor, memory: AbstractMemorySystem, cache_hierarchy: AbstractCacheHierarchy)

Bases: AbstractSystemBoard, SEBinaryWorkload

This is an incredibly simple system. It contains no I/O, and will work only with a classic cache hierarchy setup.

Limitations * Only supports SE mode

You can run a binary executable via the set_se_binary_workload function.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_dma_ports() → List[Port]

Get the board’s Direct Memory Access ports. This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

Returns:

A List of the Direct Memory Access ports.

get_io_bus() → IOXBar

Get the board’s IO Bus.

This abstract method must be implemented within the subclasses if they support DMA and/or full system simulation.

The I/O bus is a non-coherent bus (in the classic caches). On the CPU side, it accepts requests meant for I/O devices. On the memory side, it forwards these requests to the devices (e.g., the interrupt controllers on each core).

Returns:

The I/O Bus.

get_mem_side_coherent_io_port() → Port

Get the memory-side coherent I/O port.

This abstract method must be implemented if has_coherent_io is True.

This returns a port (not a bus) that should be connected to a CPU-side port for which coherent I/O (DMA) is issued.

has_coherent_io() → bool

Determine whether the board needs coherent I/O

Returns:

True if the board needs coherent I/O, False otherwise.

has_dma_ports() → bool

Determine whether the board has DMA ports or not.

Returns:

True if the board has DMA ports, otherwise False.

has_io_bus() → bool

Determine whether the board has an IO bus or not.

Returns:

True if the board has an IO bus, otherwise False.